1. Field of the Invention
The present invention relates to a data access method for a timing controller of a flat panel display and a related device, and more particularly, to a data access method and a related device for reducing memory cells of a line buffer in the timing controller, for saving memory cost for displaying images.
2. Description of the Prior Art
The advantages of a liquid crystal display (LCD) include lighter weight, less electrical consumption, and less radiation contamination. LCD monitors have been widely applied to various portable information products, such as notebooks, mobile phones, PDAs (Personal Digital Assistants), etc. In an LCD monitor, incident light produces different polarization or refraction effects when the alignment of liquid crystal molecules is altered. The transmission of the incident light is affected by the liquid crystal molecules, and thus magnitude of the light emitted from the liquid crystal molecules varies. The LCD monitor utilizes the characteristics of the liquid crystal molecules to control the corresponding light transmittance and produces gorgeous images according to different magnitudes of red, blue, and green light.
Please refer to FIG. 1. FIG. 1 is a schematic diagram of a TFT LCD device 10 according to the prior art. The TFT LCD device 10 includes a panel 100, a timing controller 102, a data-line-signal output circuit 104 and a scan-line-signal output circuit 106. The data-line-signal output circuit 104 transforms data signals into voltage signals according to related control signals generated by the timing controller 102. The scan-line-signal output circuit 106 controls output states of the voltage signals according to related control signals generated by the timing controller 102, so as to control a potential difference of an equivalent capacitor of each pixel of the panel 100 for grayscale display. In addition, a frame of an image is displayed by rows. As shown in FIG. 1, a row of a frame corresponds to 2N pixel data P1-P2N, and the 2N pixel data is outputted to the panel 100 via the two port data-line-signal output circuit 104. That is, the TFT LCD device 10 displays the pixel data P1 and PN+1 at the same time, and then displays the pixel data P2 and PN+2 at the same time, and so on.
In fact, the original 2N pixel data P1-P2N does not line up according to a displaying order of P1, PN+1, P2, PN+2 . . . , PN, and P2N. A line buffer 110 located in the timing controller 102 is utilized for transforming an original order of P1, P2 . . . , PN−1, and PN to the displaying order of P1, PN+1, P2, PN+2 . . . , PN, and P2N, and outputting to the two port data-line-signal output circuit 104. Please refer to FIG. 2 for a schematic diagram of the pixel data P1-P2N and the line buffer 110. The line buffer 110 includes N memory cells, wherein each cell is used for storing two adjacent pixel data. Therefore, the line buffer 110 can be used for storing the 2N pixel data P1-P2N. When the pixel data P1, P2 . . . , PN, and PN+1 are written into the line buffer 110, the pixel data P1 and PN+1 are read out from the line buffer 110 and outputted to the data-line-signal output circuit 104. Similarly, when the pixel data PN+2 are written into the line buffer 110, the pixel data P2 and PN+2 are read out from the line buffer 110 and outputted to the data-line-signal output circuit 104.
However, each memory cell of the line buffer 110 is used for being written and read only once, which cannot enhance the efficiency of memory cells.